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| DVIULC6-4SC6 Ultra low capacitance ESD protection Main applications DVI ports up to 1.65 Gb/s HDMI ports up to 1.65 Gb/s IEEE 1394a and IEEE 1394b ports up to 1.6 Gb/s USB2.0 ports up to 480 Mb/s (high speed), backwards compatible with USB1.1 low and full speed Ethernet port: 10/100/1000 Mb/s SIM card protection Video line protection SOT23-6L (JEDEC MO178AB) Complies with these standards: IEC61000-4-2 level 4 - 15 kV (air discharge) - 8 kV (contact discharge) Description The DVIULC6-4SC6 is a monolithic, application specific discrete device dedicated to ESD protection of high speed interfaces, such as DVI, HDMI, IEEE 1394a and IEEE 1394b, USB2.0, Ethernet links and video lines. Its ultra low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized ESD strikes. Benefits ESD standards compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS when applicable. Allows ESD current flowing to Ground when ESD event occurs on data line Optimized rise and fall times for maximum data integrity Consistent D+ / D- signal balance: - Best capacitance matching tolerance I/O to GND = 0.015 pF for ultra low inter pair skew - Best capacitance matching tolerance I/O to I/O = 0.007 pF for ultra low intra pair skew - Matching high bit rate DVI, HDMI, and IEEE 1394 requirements Low PCB space consuming, 9mm maximum foot print Low leakage current for longer operation of battery powered devices Higher reliability offered by monolithic integration Features 4 line ESD protection Protects VBUS when applicable Ultra low capacitance: 0.6 pF at F = 825 MHz Fast response time SOT23-6L package RoHS compliant Order code Part Number DVIULC6-4SC6 Marking DL46 August 2005 www.st.com Rev 1 1/12 12 DVIULC6-4SC6 Figure 1. Functional Diagram I/O1 1 1 6 I/O4 GND 2 5 VBUS I/O2 3 4 I/O3 Table 1. Symbol Absolute Ratings Parameter At device level: IEC61000-4-2 air discharge IEC61000-4-2 contact discharge MIL STD883C-Method 3015-6 Value 15 15 25 -55 to +150 125 260 Unit VPP Peak pulse voltage kV Tstg Tj TL Storage temperature range Maximum junction temperature Lead solder temperature (10 seconds duration) C C C Table 2. Symbol IRM VBR Electrical Characteristics (Tamb = 25C) Value Parameter Leakage current Test Conditions Min. VRM = 5 V 6 12 17 0.85 0.6 0.015 VR = 0 V, F= 1 MHz VR = 0 V, F= 825 MHz 0.42 0.3 0.007 0.5 pF 1 pF Typ. Max 0.5 A V V V Unit Breakdown voltage between VBUS and GND IR = 1 mA IPP = 1 A, tp = 8/20 s Any I/O pin to GND Clamping voltage IPP = 5 A, tp = 8/20 s Any I/O pin to GND VR = 0 V, F= 1 MHz VR = 0 V, F= 825 MHz VCL Ci/o-GND Capacitance between I/O and GND Ci/o-GND Capacitance variation between I/O and GND Ci/o-i/o Capacitance between I/O Ci/o-i/o Capacitance variation between I/O 2/12 DVIULC6-4SC6 Figure 2. Line Capacitance versus line voltage (typical values) C(pF) Figure 3. Line capacitance versus frequency (typical values) C(pF) 1.0 F=825MHz Vosc=500m VRMS VBU S O PEN Tj=25 C 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 CI/O - GND 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 Vosc=30mVRMS Tj =25C VI-O/GND = 0V VBUS OPEN CI/O - GND Data line voltage (v) 0.1 0 CI/O - CI/O F(MHz) 1 10 100 1000 10000 Figure 4. Relative variation of leakage current Figure 5. versus junction temperature (typical values) S21(dB) Frequency response Attenuation IRM[Tj] / IRM[Tj=25C] 5 4 0 -2 3 2 -4 -6 Tj(C) 1 25 50 75 100 125 -8 100.0k 1.0M 10.0M 100.0M 1.0G F(Hz) 3/12 1 Surge protection DVIULC6-4SC6 Technical information 1 Surge protection The DVIULC6-4SC6 is particularly optimized to perform ESD surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow: VCL+ = VBUS + VF VCL- = - VF with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 1.4 and VT = 1.2 V. For an IEC61000-4-2 surge Level 4 (Contact Discharge: Vg=8 kV, Rg=330 ), VBUS = +5 V, and if in first approximation, we assume that: Ip = Vg / Rg = 24 A. So, we find: VCL+ = +39 V VCL- = -34 V for positive surges for negative surges Note: The calculations do not take into account phenomena due to parasitic inductances. 4/12 DVIULC6-4SC6 2 Surge protection application example 2 Surge protection application example If we consider that the connections from the pin VBUS to VCC and from GND to PCB GND are done by two tracks of 10mm long and 0.5 mm large; we assume that the parasitic inductances Lw of these tracks are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1 ns), the voltage VCL has an extra value equal to Lw.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The over voltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: VCL+ = +39 + 144 = 183 V VCL- = -34 - 144 = -178 V We can reduce as much as possible these phenomena with simple layout optimization. It's the reason why some recommendations have to be followed (see Section 3: How to ensure a good ESD protection). Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout VCL+ 183V ESD SURGE VBUS Lw +VCC VF Lw di dt Lw di dt POSITIVE SURGE VCC+VF I/O tr=1ns t VI/O Lw di dt di VCL+ = VBUS+VF+Lw dt surge >0 di surge <0 VCL- = -VF-Lw dt tr=1ns t -VF -Lw di dt NEGATIVE SURGE GND -178V VCL- 5/12 3 How to ensure a good ESD protection DVIULC6-4SC6 3 How to ensure a good ESD protection While the DVIULC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the power supply +VCC and from the VBUS pin to GND must be as short as possible to avoid over voltages due to parasitic phenomena (see Figure 6). It's often harder to connect the power supply near to the DVIULC6-4SC6 unlike the ground thanks to the ground plane that allows a short connection. To ensure the same efficiency for positive surges when the connections can't be short enough, we recommend to put close to the DVIULC6-4SC6, between VBUS and ground, a capacitance of 100nF to prevent from these kinds of overfatigue disturbances (see Figure 7). The add of this capacitance will allow a better protection by providing during surge a constant voltage. The Figure 8, Figure 9, and Figure 10 show the improvement of the ESD protection according to the recommendations described above. Figure 7. ESD behavior: optimized layout and Figure 8. add of a capacitance of 100nF ESD behavior: measurements conditions (with coupling capacitance) VCL+ ESD SURGE Lw REF2=+VCC C=100nF t ESD SURGE TEST BOARD DVIULC6-4SC6 POSITIVE SURGE I/O Vcc (+5V) VCL+ = VCC+VF surge >0 VI/O t VCL- = -VF surge <0 NEGATIVE SURGE REF1=GND VCL- C=100nF 6/12 DVIULC6-4SC6 4 Crosstalk behavior Figure 9. Remaining voltage after the Figure 10. Remaining voltage after the DVIULC6-4SC6 during positive ESD DVIULC6-4SC6 during negative ESD surge surge IMPORTANT: A main precaution to take is to put the protection device closer to the disturbance source (generally the connector). Note: The measurements have been done with the DVIULC6-4SC6 in open circuit. 4 4.1 Crosstalk behavior Crosstalk phenomena Figure 11. Crosstalk phenomena RG1 Line 1 1 VG1 + 12VG2 VG1 RG2 Line 2 RL1 VG2 RL2 2VG2 + 21VG1 DRIVERS RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when 7/12 4 Crosstalk behavior DVIULC6-4SC6 the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k). Figure 12. Analog crosstalk measurements TRACKING GENERATOR 50 50 W TEST BOARD DVIULC6 SPECTRUM ANALYSER Vg Vg Vin Vcc Vout C=100nF 50 W Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -45 dB (see Figure 13). Figure 13. Analog crosstalk results Crosstalk APLAC 7.91 User: ST Microelectronics May 20 2005 0.00 - 30.00 - 60.00 - 90.00 - 120.00 100.0k 1.0M 10.0M f/Hz 100.0M 1.0G As the DVIULC6-4SC6 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (figure 5) gives attenuation information and shows that the DVIULC6-4SC6 is well suitable for data line transmission up to 1.65 Gb/s. 8/12 DVIULC6-4SC6 5 Application examples 5 Application examples Figure 14. DVI/HDMI Digital single link application using DVIULC6-4SC6 HOST (PC, graphics cards, set-top box, DVD player) Display (LCD monitor, flat panel,display, projector) Tx0Tx0+ TMDS Transmitter RX0RX0+ DVI connector 1 1 6 1 1 6 2 5 2 5 DE TMDS Receiver DE Pixel Data Graphics Controller Clock Vsync Hsync Tx1Tx1+ Tx2Tx2+ 3 4 3 4 Pixel Data Rx1Rx1+ Rx2RX2+ Clock Vsync Hsync Display Controller 1 1 6 1 1 6 2 5 TMDS Links 2 5 3 4 3 4 TCTC+ RCRC+ Figure 15. T1/E1/Ethernet protection Tx SMP75-8 +VCC 100nF 3 1 1 2 4 5 DATA TRANSCEIVER Rx SMP75-8 6 9/12 6 PCB layout considerations DVIULC6-4SC6 6 PCB layout considerations Figure 16. DVIULC6-4SC6 PCB layout considerations ( VCC connection is application dependent) Figure 17. Foot Print Dimensions (in millimeters) 0.60 DVI Connector Side D+1 D-1 GND D+2 D-2 1 1.20 VCC C = 100nF 0.95 3.50 DVIULC6-4SC6 2.30 1.10 Figure 18. SOT23-6L Package Mechanical Data DIMENSIONS REF. E Millimeters Min. Typ. Max. Min. Inches Typ. Max. 0.057 0.004 0.051 0.02 0.008 0.120 0.069 0.037 A e b e D 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 0 1.45 0.035 0.10 0 A1 A2 b c A2 1.30 0.035 0.50 0.014 0.20 0.004 3.05 0.110 1.75 0.059 D E c H A1 L e H L 3.00 0.102 0.60 0.004 10 0 0.118 0.024 10 In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 10/12 DVIULC6-4SC6 7 Ordering information 7 Ordering information Ordering code DVIULC6-4SC6 Marking DL46 Package SOT23-6L Weight 16.7 mg Base qty 3000 Delivery mode Tape & reel 8 Revision history Date 24-Aug-2005 Revision 1 Description of Changes First Issue 11/12 8 Revision history DVIULC6-4SC6 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 12/12 |
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